A phase interpolator (PI) plays an important role in a serial-link transceiver design. A phase interpolator is a circuit that has two periodic input signals which typically have the same period of oscillation and are derived from the same source. The two input signals are commonly referred to as I and Q phases of a clock signal, which could be 90 degrees apart, for example. A conventional phase interpolator generates arbitrary phases by switching the number of I and Q components, where the total number of I and Q components is a constant, thereby reducing the number of digital-to-analog converters (DACs)
Although the use of a phase interpolator in a data receiver provides many advantages such as low power consumption and high area efficiency, it demonstrates drawbacks that limit the performance. While the hardware cost of a conventional phase interpolator is low in view of the reduced number of DACs, a conventional phase interpolator generates an output which has a large amount of nonlinearity. Such nonlinearity can be significant if the phase interpolator is followed by an amplitude sensitive circuit, such as a voltage converter circuit. Because the I and Q clock signals (such as 0 and 90 degree phases of a clock signal) are never ideal sine waves, the generated clock still demonstrates non-ideal clock phase. The nonlinearity not only increases clock jitter, but can also lead the entire clock and data recovery functionality of a circuit to fail.